IC Design Engineer
Huijing
Responsibilities:
1、ASIC architecture design, partitioning and interface definition involving MCU, flash interface, SCSI-like command protocol, high-speed serial interface
2、RTL design, floor planning, device and block level verification, synthesis, physical layout support, STA, DFT
3、LAB and FPGA validation support
Qualification:
- Above 3 years experience on IC design.
- Familiar with Verilog.
- Multiple projects experience on IC design from specification to tapout.
- Experience on Storage and Datacom protocol or FLASH interface is a plus.
- Experience on large verification testbench and bus-functional models involving systemverilog/systemC or equivalent using constrained random-driven and assertion techniques is a plus.
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