Front-end IC Design Engineer
Huijing
Responsibilities:
1、module level specification definition
2、macro-architecture design
3、RTL coding and verification
4、Knowledge of Primetime or Design Time for timing analysis
5、Co-work with other team on IC debug and mass production promotion
Qualification:
1、Strong skill on Verilog
2、Familiar with function simulation EDA tools such as: nc_verilog
3、micro-architecture design and test pattern generation
4、Familiar with Computer languages C, C++, and one script language perl or python
5、Team spirit and a good communication skill
6、Master Degree in microelectronics-related filed
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