
IC Design Engineer
Huijing
Responsibilities:
- RTL or behavior level logic coding for modules.
- Module level synthesis/timing analysis.
- Writing complete design/verification reports.
- Simulation/Verification of functionalities at both module level and top level.
- Silicon debug of the related module functionalities.
- Writing test patterns for production tests.
Qualification:
- MSEE with 3year experience of digital design.
- Good English writing and reading skills.
- Solid knowledge of digital design building blocks (Data-path, Synchronizer, FIFO...)
- Strong skills of Verilog RTL coding, verification and debug.
- Solid knowledge of EDA tools such as Cadence NC-Sim, Synopsys DC, PT, Debussy etc.
- Familiar with Computer languages C, C++, and one script language perl or python.
- Familiar with System-verilog language is a plus.
- Relevant experiences in DDR interface or MCU/FPGA design is a plus.
- Good communication skill, team work spirit, self-motivated.
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